Superscalar execution: Worked examples — Hinglish deep dive

5.3.1 · D3 · Hardware › Advanced Microarchitecture › Superscalar execution

Yeh Superscalar execution ka ek worked-examples deep dive hai. Parent note ne ek master formula derive kiya tha — ki ek superscalar core har clock tick mein kitni instructions finish karta hai. Yahan hum us formula par har tarah ka input daalenge jab tak tum bottleneck ko seedha dekh ke pehchaan na sako.

Kuch bhi compute karne se pehle, aao har symbol ko dobara samjhein, kyunki ek samajhdaar 12-saal ke bachche ko bhi pehli line se padhna aana chahiye.

Definition Symbols ke peeche ke words

Cycle — CPU clock ki ek tick, processor ki sabse chhoti time unit.
Instruction — ek command, jaise "yeh do numbers add karo".
IPC (Instructions Per Cycle) — ek tick mein kitni instructions finish hoti hain. Jitna zyada utna fast. Agar IPC = 4 hai, toh char commands har tick complete hoti hain.
==Issue width $W$ == — machine ka front kitna wide ja sakta hai: ek tick mein zyada se zyada kitni instructions fetch/decode ho sakti hain. Socho isko entrance ke doors ki sankhya ke roop mein.
Functional unit — ek chhoti machine jo ek kaam karti hai: ek adder (ALU), ek multiplier, ek memory unit (load/store), ek branch checker. Agar 3 adders hain toh 3 adds ek saath ho sakte hain.
$F_{i}$ — tumhare paas type $i$ ke kitne units hain (e.g. $F_{mem} = 2$ matlab do memory units).
$p_{i}$ — program ka woh fraction jo unit type $i$ use karta hai. Agar 30% instructions memory touch karti hain, toh $p_{mem} = 0.3$ . Saare $p_{i}$ milake 1 hote hain.
ROB (Reorder Buffer) — ek waiting room jo "in flight" instructions ko hold karta hai. Iska size woh sabse badi crowd hai jisme machine independent kaam dhundh sakti hai.
$D$ — average dependency chain length: kitni instructions ek line mein stack hain, har ek apne pehle waale ka intezaar kar rahi hai (ek RAW chain).
$L$ — average latency: ek instruction start se result tak kitne ticks leti hai.

min kyun, sum ya average kyun nahin? Kyunki chain sirf apni sabse kamzor kadi jitni hi strong hoti hai — machine apni tightest constraint se tez kabhi nahin ja sakti, isliye teen mein se sabse chhota number real speed hai. Yahi poora idea hai; neeche ke har example mein bas yahi poochha jaata hai ki kaun sa gate sabse chhota hai.

Upar teen gates dekho. Ek instruction stream (arrows) unme se kisi ek se bhi squeeze ho sakta hai. Har example mein red gate woh hai jo actually hume limit karta hai — yahi hum dhundh rahe hain.

Scenario matrix

Har superscalar-IPC problem inme se kisi ek cell mein aati hai. Neeche ke examples ko unke cell ke saath label kiya gaya hai, aur milke yeh sab cover karte hain.

#	Case class	Kya special hai	Kaun sa gate usually jeetta hai	Example
A	Front-end bound	kaafi units hain, chhota $W$	gate 1 ( $W$ )	Ex 1
B	Execution bound (memory)	ek unit type overloaded	gate 2	Ex 2
C	Execution bound (compute)	alag unit type overloaded	gate 2	Ex 3
D	Dependency bound	lambi chain, tiny ROB	gate 3	Ex 4
E	Degenerate: $p_{i} = 0$	ek unit type unused (divide-by-zero risk)	us unit ko ignore karo	Ex 5
F	Degenerate: $D = 1$ ya $L = 1$	koi chains nahin / instant results	gate 3 blow up ho jaata hai (∞)	Ex 5
G	Tie / do gates equal	boundary case	koi bhi	Ex 6
H	Real-world word problem	$p_{i}$ counts se banana padta hai	koi bhi	Ex 7
I	Exam twist: "kya fix karein?"	gate dhundho, phir improve karo	reasoning	Ex 8
J	Limiting behaviour	$W \to \infty$ ya ROB $\to \infty$	bacha hua gate	Ex 9

Examples

Worked example Example 1 — Cell A: front-end bound

Diya gaya: $W = 4$ ; 3 int ALUs, 2 FP, 2 mem, 1 branch. Mix: 40% int, 20% FP, 30% mem, 10% branch. $D = 3$ , ROB $= 128$ , $L = 2$ . Forecast: abhi guess karo — entrance bottleneck hai ya machinery?

Gate 1 (front-end): $W = 4$ . Yeh step kyun? Yeh hard ceiling hai: jitna andar aane doge usse zyada kabhi finish nahin ho sakta.
Gate 2 (execution): har type ke liye $F_{i} / p_{i}$ compute karo aur sabse chhota rakho.
- int: $3/0.4 = 7.5$
- FP: $2/0.2 = 10$
- mem: $2/0.3 = 6.67$
- branch: $1/0.1 = 10$ Yeh step kyun? Sabse busy unit demand ke relative sabko throttle karta hai, isliye $min = 6.67$ lete hain.
Gate 3 (dependency): $\frac{4 \times 128}{3 \times 2} = \frac{512}{6} = 85.3$ . Yeh step kyun? Bada ROB (128) chhoti chains ( $D = 3$ ) ko aasaani se hide kar leta hai, isliye yeh gate wide open hai.
Combine: $IPC = min (4, 6.67, 85.3) = 4$ .

Verify: answer exactly $W$ ke barabar hai, aur dono doosre gates ( $6.67$ , $85.3$ ) usse zyada hain — "front-end bound" ke saath consistent. Units: instructions/cycle. ✓ Sirf wider machine (bada $W$ ) hi help karega.

Worked example Example 5 — Cells E aur F: degenerate inputs

Diya gaya: $W = 4$ ; int $4$ , FP $2$ , mem $2$ . Mix: 70% int, 0% FP, 30% mem (koi floating point nahin!). $D = 1$ , ROB $= 128$ , $L = 1$ . Forecast: $p_{F P} = 0$ hone par FP term $F_{F P} / p_{F P}$ ka kya hoga? Aur $D = 1$ , $L = 1$ hone par gate 3 ka?

$p_{F P} = 0$ handle karo (Cell E): term $\frac{2}{0}$ undefined hai, lekin iska matlab hai "FP hume kabhi limit nahin kar sakta kyunki koi instruction usse chahti hi nahin" → isko $+ \infty$ maano aur min se drop karo. Yeh step kyun? Jis unit ko koi use nahin karta woh kabhi bottleneck nahin ban sakta; yahan divide-by-zero ek modelling artefact hai, real limit nahin.
Gate 2 (sirf used types ke liye):
- int: $4/0.7 = 5.71$
- mem: $2/0.3 = 6.67$ → min $= 5.71$ .
Gate 3 with $D = 1, L = 1$ (Cell F): $\frac{4 \times 128}{1 \times 1} = 512$ . Yeh step kyun? $D = 1$ matlab koi chains nahin (har instruction independent) aur $L = 1$ matlab instant results — dependencies essentially koi limit impose nahin karti, isliye yeh gate bahut bada hai.
Combine: $IPC = min (4, 5.71, 512) = 4$ .

Verify: $p_{F P} = 0$ ko sahi se exclude karne par, front-end $W = 4$ jeetta hai. Agar hum galti se $2/0 = \infty$ min mein daalte toh bhi 4 aata — lekin reasoning (unused units drop karo) woh hai jo exam mein chahiye. ✓

Worked example Example 7 — Cell H: real-world word problem (

$p_{i}$ khud banao) Diya gaya: 1000 instructions ka ek trace: 500 integer, 150 floating-point, 250 loads/stores, 100 branches. Machine: $W = 6$ ; 4 int, 2 FP, 2 mem, 1 branch. $D = 3$ , ROB $= 96$ , $L = 2$ . Forecast: pehle counts ko fractions mein convert karo, phir gate dhundho.

Mix banao: har count ko 1000 se divide karo. $p_{int} = 0.5, p_{F P} = 0.15, p_{mem} = 0.25, p_{br} = 0.10$ . Yeh step kyun? Formula ko raw counts nahin fractions chahiye; inhe 1 tak add hona chahiye (hote hain: $0.5 + 0.15 + 0.25 + 0.10 = 1$ ).
Gate 1: $W = 6$ .
Gate 2:
- int: $4/0.5 = 8$
- FP: $2/0.15 = 13.33$
- mem: $2/0.25 = 8$
- branch: $1/0.10 = 10$ → min $= 8$ .
Gate 3: $\frac{6 \times 96}{3 \times 2} = \frac{576}{6} = 96$ .
Combine: $IPC = min (6, 8, 96) = 6$ .

Verify: fractions 1 tak add hote hain ✓; front-end ( $W = 6$ ) tightest gate hai. Toh yeh workload is machine par front-end bound hai — faster jaane ke liye wider decoder chahiye, zyada execution units nahin. ✓

Worked example Example 8 — Cell I: exam twist "kya fix karein?"

Diya gaya: $W = 4$ ; int $3$ , FP $1$ , mem $3$ , branch $1$ . Mix: 30% int, 40% FP, 20% mem, 10% branch. $D = 3$ , ROB $= 128$ , $L = 2$ . Sawaal: bottleneck bolo aur ek sabse sasta fix batao. Forecast: kaun sa gate sabse chhota hai, aur kaun sa knob usse relieve karta hai?

Gate 1: $W = 4$ .
Gate 2:
- int: $3/0.3 = 10$
- FP: $1/0.4 = 2.5$ ← min
- mem: $3/0.2 = 15$
- branch: $1/0.1 = 10$
Gate 3: $\frac{4 \times 128}{3 \times 2} = 85.3$ .
Combine: $IPC = min (4, 2.5, 85.3) = 2.5$ .
Fix diagnose karo: limiter FP hai ( $F_{F P} / p_{F P} = 2.5$ ). Ek FP unit add karo → naya FP gate $2/0.4 = 5$ , toh naya IPC $= min (4, 5, 85.3) = 4$ . Yeh step kyun? FP ke alaawa kuch bhi improve karna (jaise mem units add karna) FP ko 2.5 par rehne dega aur kuch nahin badlega — tumhe actual sabse chhote gate ko relieve karna hoga.

Verify: fix se pehle IPC $= 2.5$ ; ek FP unit add karne ke baad IPC $= 4.0$ (ab front-end bound). Ek unit ne $60%$ speedup dilaya — sahi, targeted fix. ✓

Worked example Example 9 — Cell J: limiting behaviour (

$W \to \infty$ , ROB $\to \infty$ ) Diya gaya: Ex 2 ka hardware/mix lo (mem-bound, 60% mem, 2 mem units) lekin imagine karo infinitely wide front-end ( $W \to \infty$ ) aur infinite ROB. Forecast: front-end gate aur dependency gate dono hat jaane par kya rokta hai?

Gate 1 ( $W \to \infty$ ): hat gaya, ab min mein nahin.
Gate 3 (ROB $\to \infty$ ): $\frac{W \cdot ROB}{D L} \to \infty$ : yeh bhi hat gaya.
Sirf gate 2 bachta hai: mem $= 2/0.6 = 3.33$ . Yeh step kyun? Infinite machine hone par bhi sirf 2 memory units hain; 60% instructions unhe chahti hain, isliye $0.6 \cdot IPC \leq 2$ .
Combine: $IPC = min (\infty, 3.33, \infty) = 3.33$ .

Verify: physical execution resource ultimate ceiling hai — hardware shortage ko out-fetch nahin kar sakte. Ex 2 ke answer (3.33) se exactly match karta hai, confirm karta hai ki memory wahan real limiter thi, width nahin. ✓

Recall Quick self-test

Front-end bound matlab IPC kis symbol ke barabar hota hai? ::: $W$ (issue width) Agar kisi unit type ke liye $p_{i} = 0$ ho, toh uske $F_{i} / p_{i}$ term ka kya karo? ::: Drop karo — unused unit kabhi bottleneck nahin ban sakta; ratio undefined hai ( $\infty$ ). $\frac{W \cdot ROB}{D \cdot L}$ kaun sa gate hai? ::: Dependency gate (gate 3); lambi chains $D$ aur high latency $L$ se shrink hota hai, bade ROB window se badhta hai. Balanced design mein do gates equal hote hain — isko improve karna kyun mushkil hai? ::: Ek ko relieve karne par doosra same value par rehta hai, isliye speed gain ke liye dono improve karne padte hain. Ek workload 60% memory hai aur 2 mem units hain. IPC ki hard ceiling kya hai? ::: $2/0.6 = 3.33$ , chahe machine kitni bhi wide ho.

Dekho bhi: Tomasulo's Algorithm, Branch Prediction, Cache Hierarchy, VLIW Architecture, Power-Performance Tradeoffs.