Superscalar execution: Visual walkthrough — Hinglish deep dive

5.3.1 · D2 · Hardware › Advanced Microarchitecture › Superscalar execution

Shuru karne se pehle, teen words plain English mein (hum har symbol ko earn karte jaayenge):

Step 1 — Highway ka picture banao: "superscalar" actually kaisa dikhta hai

KYA HAI. Ek plain (scalar) processor ek single-lane road hai: ek tick mein ek instruction aage badhti hai. Ek superscalar processor ek multi-lane highway hai: kai instructions ek hi tick mein aage badhti hain.

KYUN. Is page par sab kuch ek finish line cross karne waali cars ko count karne ke baare mein hai. Isliye pehle humein road ka picture chahiye. Lanes ki sankhya ka ek naam hai.

PICTURE. Neeche: chaar lanes, chaar cars saath milke chalti hain. Daayein taraf dashed finish line "retire" hai — jahaan ek instruction officially done count hoti hai. Ek tick mein cross karne waali cars count karo aur tumhare paas IPC hai.

Abhi, bina kisi obstacle ke, saari 4 lanes full hain, isliye IPC = 4 hai. Yeh hamara pehla ceiling hai, aur sabse simple:

Dekho Register Renaming aur Tomasulo's Algorithm us machinery ke liye jo un lanes ko feed rakhti hai.

Step 2 — Cars ko sahi tarah ka exit chahiye: functional units

KYA HAI. Har instruction same nahi hoti. Kuch integer adds hain, kuch memory loads hain, kuch floating-point hain. Har type ko door ke aakhri end par ek matching machine use karni padti hai, jise functional unit kehte hain.

KYUN. Yahan woh catch hai jo doosra ceiling create karta hai. Agar tumhari zyaatar cars saari ek hi exit chahti hain, aur wahan sirf do hi hain, toh cars pile up ho jaati hain — chahe baaki exits khali hi kyun na hon.

PICTURE. Neeche, teen exit types (integer ×3, memory ×2, FP ×2). Saari laal memory-cars do memory exits chahti hain. Extra memory cars ko wait karna padta hai, isliye highway jam ho jaati hai chahe FP exits khali hon.

Is picture ko ek number mein convert karne ke liye humein ek aur word chahiye: kitni baar har exit chahiye hoti hai.

Step 3 — Har exit kitni baar chahiye? Instruction mix $p_{i}$

KYA HAI. Ek program ke lambe run mein, har type ki instructions ka ek fixed fraction hota hai.

KYUN. Agar main ek cycle mein $X$ instructions push karna chahta hoon, toh unme se $p_{i} \cdot X$ har cycle mein type $i$ unit demand karengi. Lekin type $i$ sirf $F_{i}$ per cycle serve kar sakti hai. Isliye mujhe kabhi bhi ussi se zyada nahi maangna chahiye jo woh de sakti hai: $p_{i} \cdot X \leq F_{i} ⟹ X \leq \frac{F _{i}}{p _{i}}$

Aao is final ratio ko term by term padhte hain:

$instr/cycle jo main chahta hoon X \leq \frac{F _{i} type i ki units}{unhe chahne waala fraction p _{i}}$

PICTURE. Har type ke liye ek bar. Bar ki height us type ki ceiling $F_{i} / p_{i}$ hai. Sabse chhota bar asli wall hai — woh exit jo pehle jam hoti hai.

Step 4 — Degenerate case: agar koi exit type kabhi use hi na ho?

KYA HAI. Maano ek program mein zero floating-point instructions hain: $p_{FP} = 0$ .

KYUN. Formula mein $p_{i}$ denominator mein hai, aur zero se divide karna undefined hai. Kya FPUs achanak humein infinity tak limit kar dete hain? Nahi — physics ulta kehta hai: ek exit jisko koi nahi chahta woh kabhi bottleneck nahi ban sakti.

PICTURE. FP bar ki height $F_{FP} /0 = + \infty$ hai — woh chart ke top se upar shoot kar jaata hai. Ek infinitely tall bar kabhi sabse chhota bar nahi ho sakta, isliye $min_{i}$ use simply ignore kar deta hai. Yahi correct behaviour hai.

Step 5 — Hidden rope: dependency chains

KYA HAI. Kuch instructions ko pehle wali ke result ka wait karna padta hai. Woh MUL jo R1 read karta hai, tab tak start nahi ho sakta jab tak ADD jo R1 produce karta hai finish na ho jaaye. Yeh ek RAW (Read-After-Write) dependency hai — do cars ko aapas mein baandhne waali rope.

KYUN. $D$ roped cars ki ek chain, jisme se har ek $L$ cycles leti hai, clear hone mein $D \cdot L$ cycles lagti hai — aur us time mein woh cars single file mein phans jaati hain. Highway ko busy rakhne ke liye CPU ko aage dekhna padta hai, independent cars dhundhni padti hain, aur unhe chalana padta hai jab roped wali wait kar rahi hain. Woh kitna aage dekh sakta hai woh uske waiting room ka size hai.

Har cycle machine $ROB$ size ke ROB mein $W$ naye instructions pull karti hai. Pool puri tarah $ROB / W$ ... mein refresh hota hai lekin parent jo useful bound deta hai woh hai:

$IPC \leq \frac{W lanes \cdot ROB waiting room}{rope length D \cdot cycles each L}$

Ise ek tug-of-war ki tarah padho: ek bada waiting room ( $ROB$ ) aur wide fetch ( $W$ ) ceiling ko upar push karte hain (fraction ka top); lambi ropes ( $D$ ) aur slow instructions ( $L$ ) ise neeche kheenchte hain (fraction ka bottom).

PICTURE. Baayein taraf $D$ roped cars ki single-file rope (woh dhheere chalti hain), aur daayein taraf ek bada ROB pool unroped cars se bhara hai jise CPU IPC high rakhne ke liye meanwhile run karta hai.

Step 6 — Teen walls ko saath mein rakho: $min$ kyun?

KYA HAI. Ab hamare paas teen alag ceilings hain. Real IPC teeno mein se sabse chhoti hai.

KYUN. Machine ko teen sections waale pipe ki tarah socho jisme alag-alag widths hain: front door ( $W$ ), exits ( $min_{i} F_{i} / p_{i}$ ), aur rope-limited window ( $W \cdot ROB / (D \cdot L)$ ). Paani sirf utni tez flow kar sakta hai jitni sabse narrow section allow karti hai. Kisi doosri section ko wide karne se kuch nahi hota. "Narrowest wins" exactly wohi hai jo $min$ ka matlab hai.

PICTURE. Alag-alag heights ki teen walls. Ek horizontal red line sabse chhoti wall ki height par hai — woh line tumhara actual IPC hai. Us line ke upar sab kuch wasted capacity hai.

Step 7 — Do full walkthroughs, edge behaviour samet

Ek-picture summary

Neeche: poori derivation ek single canvas par. Teen walls (front door, exits, rope-window); red finish-line sabse chhoti par baithi hai; woh height IPC hai. Line ke upar sab kuch idle silicon hai.

Recall Feynman retelling — plain words mein bol ke dikhao

Socho chip ke andar ek multi-lane highway hai. Lanes ki sankhya $W$ hai — yeh sabse zyada cars hain jo tum har tick start kar sakte ho. Door ke doosre end par alag-alag tarah ke exits hain (integer, memory, FP); agar bahut saari cars same thodi si exits chahti hain, woh jam ho jaati hain — woh jam limit $F_{i} / p_{i}$ hai, aur sabse busy exit ( $min_{i}$ ) decide karti hai. Aur kuch cars ropes se baandhi hoti hain aur sirf single file mein ja sakti hain; CPU ise is tarah chhupata hai ki ek bada waiting room (ROB) unroped cars se bhara rakhta hai jo meanwhile run hotin hain — isse $W \cdot ROB / (D \cdot L)$ milta hai. Tumhari real speed in teeno mein se sabse narrow set karti hai, exactly isliye formula teen cheezein ka $min$ hai. Agar koi exit kabhi use nahi hoti ( $p_{i} = 0$ ), uski limit infinite hai, isliye use simply ignore kar diya jaata hai.

Recall Quick self-test

Master formula $min$ kyun hai, sum ya product kyun nahi? ::: Ek chain sirf apni sabse kamzor link jitni mazboot hoti hai — ek pipe mein flow uske sabse narrow section se set hota hai, isliye sabse tight ceiling IPC decide karti hai. Agar $p_{FP} = 0$ ho, toh us exit ki ceiling kya hai aur kya woh bind karti hai? ::: $F_{FP} /0 = \infty$ ; ek infinite ceiling kabhi sabse chhoti nahi ho sakti, isliye woh kabhi bind nahi karti. Machine fetch-bound hai IPC = $W$ par. Kya load/store units add karne se help hogi? ::: Nahi — Ceiling #1 wall hai; tumhe instead $W$ badhana hoga. Ceiling #2 kaun sa single ratio hai, aur kaun sa type use set karta hai? ::: $min_{i} F_{i} / p_{i}$ ; woh type jiska units-to-demand ratio sabse chhota hai (sabse busy, sabse kam served exit).