Superscalar execution — Hinglish notes

5.3.1 · Hardware › Advanced Microarchitecture

Ek Processor ko Superscalar Kya Banata Hai?

Width Parameter

Issue width N determine karta hai ki ek cycle mein kitne instructions dispatch ho sakte hain. Common values:

2-way superscalar: 2 instructions/cycle (purana Intel Pentium)
4-way superscalar: 4 instructions/cycle (Intel Core)
6-8 way superscalar: Modern high-performance cores (Intel Skylake, AMD Zen)

Superscalar Execution Kaise Kaam Karta Hai: Pipeline Stages

1. Instruction Fetch (Width N)

Kya hota hai: Ek cycle mein cache se N instructions fetch karo.

Yeh mushkil kyun hai: Instruction stream hamesha achhi tarah aligned nahi hoti. Agar tumhe 4 instructions fetch karni hain lekin woh ek cache-line boundary ke across hain, toh tumhe do cache accesses chahiye ho sakte hain.

Kaise solve hota hai:

Wide instruction cache ports
Branch predictors jo aage multiple branches predict karte hain
Fetched instructions queue karne ke liye instruction buffers

2. Decode (Width N)

Kya hota hai: N instructions ko simultaneously micro-ops mein decode karo.

Yeh mushkil kyun hai: x86 instructions ki length variable hoti hai (1-15 bytes). Parallel mein multiple instructions ke liye instruction boundaries dhundhna complex hai.

Kaise solve hota hai:

Cache lines mein pre-decode bits add karna
Pehli kuch positions ke liye complex decoders
Baaki positions ke liye simpler decoders
Modern designs mein micro-op cache (decoded instruction cache)

3. Rename and Dispatch

Kya hota hai: False dependencies eliminate karne ke liye architectural registers ko physical registers mein rename karo, phir reservation stations mein dispatch karo.

Yeh kis problem ko solve karta hai:

ADD R1, R2, R3  ; R1 = R2 + R3
MUL R4, R1, R5  ; R4 = R1 * R5  (needs R1, has RAW dependency)
ADD R1, R6, R7  ; R1 = R6 + R7  (WAW hazard with first instruction)
SUB R8, R1, R9  ; R8 = R1 - R9  (which R1? WAR hazard)

Rename solution:

ADD P10, P2, P3   ; Rename R1 → P10
MUL P11, P10, P5  ; Uses P10, can execute when P10 ready
ADD P12, P6, P7   ; Rename R1 → P12 (different physical register!)
SUB P13, P12, P9  ; Uses P12, no confusion

Ab instructions 1 aur 3 mein false dependency nahi hai—woh alag physical registers mein likhte hain.

4. Issue (Out-of-Order)

Kya hota hai: Instructions reservation stations mein wait karti hain jab tak unke operands ready nahi ho jaate, phir execution units ko issue hoti hain.

Key insight: Instructions program order mein issue nahi hoti. Woh tab issue hoti hain jab:

Functional unit available ho
Saare source operands ready hon
Koi structural hazard na ho

Yahi out-of-order execution hai.

5. Execute (Multiple Units)

Kya hota hai: Multiple functional units parallel mein instructions execute karte hain.

Ek typical superscalar mein ho sakta hai:

4 integer ALUs
2 load/store units (AGU + data port)
2 floating-point units
1 branch unit

Throughput vs Latency:

Integer ADD: 1 cycle latency, 4/cycle throughput (4 units)
Integer MUL: 3 cycle latency, 1/cycle throughput (1 unit)
FP DIV: 20 cycle latency, 1/20 cycle throughput (1 unit, not pipelined)

6. Retire (In-Order, Width N)

Kya hota hai: Reorder buffer (ROB) ensure karta hai ki instructions apne results program order mein commit karein, precise exceptions maintain karte hue.

In-order retirement kyun: Agar exception aata hai, toh faulting instruction se pehle ki saari instructions complete honi chahiye, aur baad wali instructions ka koi visible effect nahi hona chahiye.

Derivation: Maximum IPC

Chaliye theoretical maximum instructions per cycle (IPC) derive karte hain.

Diya gaya:

Issue width: $W$
Functional units ki sankhya: type $i$ ke $F_{i}$
Instruction mix: fraction $p_{i}$ ko unit type $i$ chahiye
Average instruction latency: $L$

Step 1: Maximum fetch/decode rate = $W$ instructions/cycle

Step 2: Dependencies ki wajah se maximum issue rate limited hoti hai. Perfect register renaming aur infinite ROB ke saath, yeh limited hoti hai: $Issue rate \leq min (W, functional unit throughput)$

Step 3: Functional unit throughput: Type $i$ ke $F_{i}$ units ke saath: $Throughput_{i} = F_{i} instructions/cycle$

Step 4: Instruction mix ko consider karte hue overall throughput: Agar $p_{i}$ fraction instructions ko unit type $i$ chahiye: $IPC_{max} = min (W, min_{i} \frac{F _{i}}{p _{i}})$

Yeh step kyun?: Agar 50% instructions load/store hain ( $p_{mem} = 0.5$ ) aur tumhare paas 2 load/store units hain ( $F_{mem} = 2$ ), toh memory operations tumhe maximum $\frac{2}{0.5} = 4$ IPC tak limit karti hain.

Step 5: Dependency limit. Agar average dependency chain length $D$ hai aur latency $L$ hai: $IPC_{dependency} \leq \frac{W \cdot Window size}{D \cdot L}$

Final formula: $IPC = min (W, i min \frac{F _{i}}{p _{i}}, \frac{W \cdot R O B _ s i z e}{D \cdot L _{avg}})$

Worked example Worked Example: 4-way Superscalar IPC

Diya gaya:

4-way superscalar ( $W = 4$ )
3 integer ALUs, 2 FPUs, 2 load/store units
Instruction mix: 40% integer, 20% FP, 30% load/store, 10% branch
Average dependency chain: 3 instructions
ROB size: 128 entries
Average latency: 2 cycles Solution: Fetch/decode limit: 4 instructions/cycle Functional unit limits:
Integer: $\frac{3}{0.4} = 7.5$ IPC
FP: $\frac{2}{0.2} = 10$ IPC
Memory: $\frac{2}{0.3} = 6.67$ IPC
Branch: $\frac{1}{0.1} = 10$ IPC

Minimum FU limit = 6.67 IPC Dependency limit: $\frac{4 \times 128}{3 \times 2} = \frac{512}{6} = 85.3 IPC$ (Bade ROB ke saath dependencies humein limit nahi karti)

Final IPC: $min (4, 6.67, 85.3) = 4$ IPC

Kyun? Fetch/decode width of 4 bottleneck hai. Hamare paas enough functional units hain aur dependencies hide karne ke liye large enough window bhi hai. Wider design se faida hoga.

Superscalar ke liye Critical Structures

Reorder Buffer (ROB)

Kya hai: Circular buffer jo in-flight instructions ko program order mein track karta hai.

Kyun: Out-of-order execution ko in-order retirement ke saath enable karta hai (precise exceptions).

Kaise: Har ROB entry mein hota hai:

Instruction ka PC
Destination register (logical)
Result value ya physical register ka pointer
Status (pending/complete)
Exception flags

Size matters: $Max instructions flight = ROB size$

Bada ROB → independent kaam dhundhne ke liye zyada instructions → higher IPC, lekin zyada complex hardware.

Register Alias Table (RAT)

Kya hai: Architectural registers ko physical registers mein map karta hai.

Size: $R$ architectural registers aur $P$ physical registers ke liye:

RAT entries: $R$ (har architectural register ke liye ek)
Har entry: $⌈ lo g_{2} P ⌉$ bits

Kyun: WAW aur WAR hazards eliminate karta hai, zyada parallelism enable karta hai.

Example: x86-64 mein 16 integer registers hain. Ek modern design mein 180 physical registers ho sakte hain. $RAT size = 16 \times ⌈ lo g_{2} 180 ⌉ = 16 \times 8 = 128 bits$

Reservation Stations

Kya hain: Buffers jo operands ka wait kar rahi instructions ko hold karte hain.

Kyun: Instruction issue ko execution se decouple karte hain, instructions ko dispatch block kiye bina wait karne dete hain.

Key property: Instructions tab wake up hoti hain jab unka last operand ready ho jaata hai (associative search).

Limitations aur Tradeoffs

Common mistake Common Misconception: "N-way superscalar N× speedup deta hai"

Kyun sahi lagta hai: Agar tum N cheezein ek saath kar sako, toh N guna fast hona chahiye.

Kyun galat hai:

Dependencies: True RAW dependencies parallelism limit karti hain. Lambi dependency chains execution serialize kar deti hain.
Structural hazards: Instruction mix ke liye enough functional units nahi hain.
Control hazards: Branches instruction stream interrupt karte hain.
Memory bottlenecks: Cache misses sab kuch stall kar dete hain.

Reality: Ek 4-way superscalar real code pe typically 2-3 IPC achieve karta hai (50-75% efficiency).

Steel-man the mistake: N× assumption embarrassingly parallel workloads ke liye valid hai jahan koi dependencies nahi hain, jaise SIMD vector operations. Lekin control flow code mein inherent dependencies hain.

Fix: Samjho ki IPC instruction stream ki inherent parallelism se limited hai, sirf hardware width se nahi. Amdahl's Law apply hota hai: agar sirf 50% code parallel chal sakta hai, toh infinite width bhi zyada se zyada 2× speedup deti hai.

Recall Superscalar ko 12-Saal ke Bachche ko Explain Karo

Socho tum homework kar rahe ho. Tumhare paas kaafi problems solve karni hain: math problems, reading comprehension, aur ek picture banana.

Normal computer (scalar): Tumhare paas ek desk hai. Tum ek waqt mein ek problem karte ho. Math problem → reading → drawing → agli math problem. Agla shuru karne se pehle pehla khatam karna padta hai.

Pipelined computer: Tum phir bhi ek waqt mein ek karte ho, lekin jaise hi math problem padhna khatam karo, pehla solve karte waqt agla padh sakte ho. Jaise assembly line.

Superscalar computer: Ab tumhare paas TEEN desks aur tumhare teen copies hain! Ek math kar sakta hai, ek padh sakta hai, aur ek draw kar sakta hai—sab ek saath! Lekin ek catch hai: agar drawing ko math problem ka answer chahiye, toh wait karna padega. Saath hi, tumhare paas sirf ek pencil sharpener hai, toh agar teeno ko pencil sharpen karni hai, do ko wait karna padega.

Yahi superscalar hai: ek saath multiple cheezein karna, lekin tabhi jab woh ek doosre par depend na karti hon aur tumhare paas sabke liye enough tools hon.

Connections

Instruction-Level Parallelism: Superscalar ILP exploit karne ki primary technique hai
Register Renaming: False dependencies eliminate karne ke liye essential hai
Out-of-Order Execution: Superscalar processors typically OoO execute karte hain
Branch Prediction: Pipeline ko instructions se feed rakhne ke liye critical hai
Tomasulo's Algorithm: Superscalar ke liye classic dynamic scheduling algorithm
Reorder Buffer: Out-of-order superscalar mein precise exceptions maintain karta hai
VLIW Architecture: Alternative approach jahan compiler instruction scheduling karta hai
Cache Hierarchy: Multiple memory ops/cycle ke liye sufficient bandwidth provide karna zaroori hai
Power-Performance Tradeoffs: Wider superscalar matlab zyada power consumption

#flashcards/hardware

Superscalar processor kya hota hai? :: Ek processor jo ek hi clock cycle mein multiple functional units aur dynamic scheduling use karke multiple instructions simultaneously fetch, decode, aur execute kar sakta hai.

Data dependencies ke teen types kya hain?

RAW (Read After Write - true dependency), WAW (Write After Write - false/output dependency), WAR (Write After Read - false/anti-dependency).

Architectural registers ko physical registers ke ek bade pool mein map karke, taaki ek hi architectural register mein likhne wali do instructions actually alag physical registers mein likhein, WAW aur WAR hazards eliminate ho jaate hain.

Reorder Buffer (ROB) ka purpose kya hai?

In-flight instructions ko program order mein track karna aur ensure karna ki woh order mein retire (commit) karen, precise exceptions maintain karte hue, bhale hi execution out-of-order ho.

Superscalar processors mein in-order retirement kyun zaroori hai?

Precise exceptions maintain karne ke liye—agar exception aata hai, toh faulting instruction se pehle ki saari instructions complete honi chahiye aur baad wali instructions ke koi visible architectural effects nahi hone chahiye.

Superscalar processor ki IPC kya limit karta hai?

In mein se minimum: fetch/decode width, instruction type ke hisaab se functional unit throughput, aur instruction window size divided by average dependency chain length times latency.

Superscalar processor ki issue width kya hoti hai?

Maximum number of instructions jo ek single clock cycle mein functional units ko dispatch ki ja sakti hain (jaise, 4-way superscalar 4 instructions/cycle issue kar sakta hai).

Reservation stations out-of-order execution kaise enable karte hain? :: Woh operands ka wait kar rahi instructions ko buffer karte hain aur unhe functional units ko tab issue karte hain jab operands ready ho jaate hain aur units available hoti hain, dispatch ko execution se decouple karke.

Functional units ke liye throughput aur latency mein kya difference hai?

Latency yeh hai ki ek operation kitne cycles leta hai; throughput yeh hai ki processor kitne operations per cycle start kar sakta hai (multiple units ya pipelining ke saath 1/latency se zyada ho sakta hai).

N-way superscalar processors N× speedup kyun achieve nahi karte?

True data dependencies, control hazards (branches), structural hazards (limited functional units), aur memory bottlenecks ki wajah se—real code 50-75% efficiency achieve karta hai.