Superscalar execution: Foundations — Hinglish deep dive

5.3.1 · D1 · Hardware › Advanced Microarchitecture › Superscalar execution

Parent note Superscalar execution padhne se pehle, tumhe har woh symbol dikhna chahiye jo woh tumhare saamne phenkata hai. Neeche, har idea zero se banaya gaya hai: plain words → ek picture → is topic ko yeh kyun chahiye. Upar se neeche padho; har block uske upar wale pe lean karta hai.

1. Ek "clock cycle" — dhadkan

Picture. Ek drummer ko steady beat rakhte hue imagine karo. Har beat pe gates khulte hain aur kaam ek step aage badhta hai. Beat kabhi bhi mid-song mein speed up nahi hoti — pura design fixed-length ticks ke around bana hai.

Figure s01 — walkthrough. Pale-yellow square wave clock signal hai; yeh "low" aur "high" ke beech snap karta hai. Har dotted blue vertical line rising edge mark karti hai jo ek nayi tick shuru karti hai, aur pink labels ("tick 1", "tick 2", …) unhe count karte hain. Blue lines ke beech spacing har jagah identical hai — yeh fixed width poora point hai: ek cycle time ki ek unit hai jo tum count kar sakte ho.

Topic ko yeh kyun chahiye. Har cheez "per cycle" count hoti hai: instructions fetched per cycle, retired per cycle. Agar tumhe tick picture nahi hoti, toh " $4$ instructions per cycle" jaise phrases bas shor hain.

2. Ek "instruction" aur "pipeline" — assembly line

Picture. Stations ke saath ek single conveyor belt. Har station pe ek car. Har tick pe ek car end se nikalta hai.

Figure s02 — walkthrough. Grid ko columns = clock cycles (c1…c8, bottom axis) aur rows = pipeline stages (Fetch, Decode, Exec, Write, left axis) ke roop mein padho. Har coloured box ek instruction label (I1…I4) rakhta hai. Instruction I1 ko diagonal staircase pe follow karo: yeh c1 mein Fetched hoti hai, c2 mein Decoded, c3 mein Executed, c4 mein Written. Staircase shape ka matlab hai ki pipe ke andar ek waqt mein chaar instructions hamesha hoti hain — lekin "Write" row trace karo: ek hi box har column mein land karta hai (pink arrow isko point karta hai). Yahi pipeline ki hard limit hai: time mein overlap, phir bhi har tick pe sirf ek finish.

Topic ko yeh kyun chahiye. Superscalar plain pipeline ke against define hota hai. Plain pipeline abhi bhi har tick pe sirf ek instruction khatam karti hai. Parent note ka poora point yeh hai: agar hum kai belts side by side chalayein toh?

3. IPC — woh score jiske peechhe hum hain

Ek plain pipeline: $IPC \leq 1$ (zyada se zyada har tick pe ek).
Ek $4$ -wide superscalar: $IPC$ $4$ ke kareeb ja sakta hai.

Topic ko yeh kyun chahiye. Parent ka poora "Derivation: Maximum IPC" is number ke ceiling ke baare mein hai. Har limit (units, width, dependencies) ek reason hai ki IPC ideal se neeche kyun girta hai.

4. Symbol $W$ — issue width

Picture. Ek ki jagah chaar belts side by side. Har tick pe chaar cars enter karti hain.

Yeh kai independent ceilings mein se hamari pehli hai. Isse yaad rakho — hum teen collect karenge aur unhe end mein combine karenge.

5. Functional units aur symbols $F_{i}$ , $p_{i}$

Subscript $i$ bas ek label hai ("ALU", "FP", "mem", "branch"). Yeh koi number nahi hai.

Figure s03 — walkthrough. Har bar ek unit type hai; uski height ceiling

F_{i} / p_{i}

(instructions/cycle) hai, jo upar print ki gayi hai. ALU bar padho:

3

units

40%

demand serve kar rahi hain toh

3/0.4 = 7.5

. Ab sabse chhote bar ko dhundo — yahan pink mein outlined, memory unit

6.67

pe. Woh sabse chhota bar traffic jam hai: chahe baaki kitne bhi tall hon, poori machine utni hi fast flow kar sakti hai jितनी uski sabse zyada-strained unit type. Pink arrow isse "bottleneck = smallest F/p" label karta hai.

Ab is ceiling ko formal banate hain, upar wale width ceiling se match karte hue.

6. Dependencies — RAW, WAW, WAR (kyun order matter karta hai)

Do instructions tab hi ek saath chal sakti hain jab woh ek doosre ko step on na karein. Teen tarike hain jinse woh clash kar sakti hain, ek register $R_{k}$ (ek named storage slot, jaise $R 1$ ) use karke.

Figure s04 — walkthrough. Teen chhote stacked pairs hain, har ek instruction A upar instruction B ke saath register

R 1

share karte hue. Left, blue (RAW): yellow arrow A→B run karta hai kyunki B ko literally woh value chahiye jo A ne produce ki — labelled TRUE. Lower-left, pink (WAW): dono

R 1

likhte hain; yeh sirf naam pe clash karte hain — labelled false. Right, off-white (WAR): A

R 1

read karta hai phir B isse overwrite karta hai — phir se false. Neeche blue note punchline hai: doosre writer ko ek fresh name dedo aur dono false clashes gayab ho jaate hain.

"True" vs "false" kyun matter karta hai. RAW real data flow hai — koi trick isse remove nahi karti. WAW aur WAR sirf isliye exist karte hain kyunki humne ek register name reuse kiya. Doosre writer ko ek fresh name do aur clash gayab ho jaata hai. Woh trick hai Register Renaming.

Topic ko yeh kyun chahiye. Poora "Rename and Dispatch" stage, aur parent ka dependency-chain length $D$ , inhi hazards ke baare mein hain.

7. ROB — instructions ka "waiting room"

Parent ka dependency ceiling likhne se pehle humein ek aur symbol chahiye: woh buffer ka size jo in-flight instructions hold karta hai.

Picture. Ek ticket queue: log kisi bhi order mein serve (compute) hote hain, lekin door se ek-ek karke us order mein nikalte hain jisme aaye the — toh bahar se sab kuch orderly lagta hai. $R_{ob}$ yeh hai ki queue kitne tickets hold kar sakti hai.

Topic ko yeh kyun chahiye. Bada ROB = independent kaam dhundhne ke liye badi window = higher IPC. Isliye $R_{ob}$ agle section mein bane IPC formula ke andar baith ta hai.

8. $D$ aur $L$ — chain length aur latency

Dependency ceiling step by step derive karte hain. Ab hamare paas parent ki teesri ceiling banane ke liye har symbol hai. Yeh abhi bhi ordinary IPC (section 3) hai, lekin ek specific limit ke under compute kiya gaya: independent kaam ki supply.

Formula Dependency ceiling — derived

Step 1 — ek waqt mein kitne slots of work available hain? Machine har cycle $W$ tak instructions fetch karti hai aur unhe $R_{ob}$ in flight mein hold kar sakti hai. Ek poori window ke lifetime mein, total pool of instruction-slots jo usne stage ki hain woh hai $slots available = W \cdot R_{ob} .$ Step 2 — ek dependency chain kitne slots tie up karti hai? $D$ length ki ek RAW chain khud ke saath overlap nahi kar sakti; uski har $D$ instructions $L$ cycles leti hai apna result produce karne mein, isliye chain khatam karna occupy karta hai $slots occupied per chain = D \cdot L$ cycle-slots jo strictly in order run hone pe majboor hain. Step 3 — available ko occupied se divide karo. Chains ki number jo hum per cycle flowing rakh sakte hain — aur isliye woh IPC ceiling jo dependencies allow karti hain — pool ko per-chain cost se divide karna hai: $IPC_{dependency} \leq \frac{W \cdot R _{ob}}{D \cdot L} .$

Shape padho: ek longer chain ( $D$ big) ya slower ops ( $L$ big) ceiling ko chhota karte hain; ek bigger ROB ( $R_{ob}$ big) isse bada karta hai zyada independent kaam overlap karne ke liye. Yeh teesri aur last ceiling hai.

9. Control-flow dependencies — branch ceiling

Ek aur tarika hai stall karne ka jo bilkul bhi RAW/WAW/WAR nahi hai.

Kyun yeh apni khud ki ceiling hai. Ek misprediction poori pipeline empty kar deta hai aur correct target se re-fetch karta hai, ek fixed number of cycles waste karta hai (misprediction penalty). Jitne zyada branches, aur prediction jitni kharab, utni baar wide fetch engine dry run karta hai. Toh perfect units aur infinite ROB ke saath bhi, control flow IPC ko cap karta hai:

10. Ceilings combine karna — minimum kyun?

Humne teen independent ceilings collect ki hain, har ek ek true upper bound hai jo apne aap hold karni chahiye:

$IPC \leq W, IPC \leq min_{i} \frac{F _{i}}{p _{i}}, IPC \leq \frac{W \cdot R _{ob}}{D \cdot L} .$

Prerequisite map

Har foundation IPC score mein flow karti hai, aur IPC score wahi hai jiske liye parent note ek ceiling derive karta hai.

Jab yeh symbols solid ho jayein, toh inhe implement karne wali machinery inme rehti hai: Register Renaming · Tomasulo's Algorithm · Reorder Buffer · Branch Prediction · Cache Hierarchy · VLIW Architecture · Power-Performance Tradeoffs. Aur Hindi walkthrough: 5.3.01 Superscalar execution (Hinglish).

Equipment checklist

Sawaal padho, zyaaz se jawab do, phir reveal karo.

Clock cycle kya represent karta hai?

CPU ke metronome ki ek tick; saara kaam per tick measure hota hai.

Plain pipeline aur superscalar mein kya fark hai?

Pipeline instructions ko time mein overlap karta hai (max 1 finish/tick); superscalar multiple belts chalata hai taaki kai instructions same stage share karein aur kai per tick khatam hon.

IPC ek sentence mein define karo.

CPU jo average number of instructions per clock cycle khatam karta hai.

Symbol

W

kya hai aur yeh IPC pe kya ceiling lagata hai?

Issue width — instructions started per cycle; tum kabhi shuru se zyada khatam nahi kar sakte, isliye

IPC \leq W

F_{i}

aur

p_{i}

kya matlab rakhte hain, aur

\sum_{i} p_{i}

kya satisfy karna chahiye?

F_{i}

= type

i

ke functional units ki number;

p_{i}

= us type ko zaroori instructions ka fraction; classes disjoint hain isliye

\sum_{i} p_{i} \leq 1

Unit ceiling

F_{i} / p_{i}

ek division kyun hai, aur yeh kahaan se aata hai?

p_{i} x \leq F_{i}

se (demand supply se zyada nahi ho sakta), jo deta hai

x \leq F_{i} / p_{i}

; supply over demand-fraction.

Teen hazards ka naam batao aur kaun se false hain.

RAW (true), WAW (false), WAR (false); false wale register renaming se gayab ho jaate hain.

Symbol

R_{ob}

kya stand karta hai?

Reorder buffer ka size — ek waqt mein kitni instructions in flight mein ho sakti hain.

D

aur

L

kya stand karte hain?

D

= RAW dependency chain ki length;

L

= ek instruction ko apna result produce karne mein kitne cycles lagte hain.

Dependency ceiling mein, available slots vs occupied slots kya count hota hai?

W \cdot R_{ob}

= staged instruction-slots available;

D \cdot L

= ek in-order chain ke cycle-slots jo occupy hote hain.

Teen ceilings minimum ke saath combine kyun hoti hain?

Har ek ek upper bound hai jo ek saath hold karni chahiye, isliye IPC sabse chhote se zyada nahi ho sakta — tightest bound jeeta hai.

RAW/WAW/WAR ke alawa, kaunsi aur dependency IPC cap karti hai?

Control-flow (branch) dependencies — mispredictions pipeline flush karte hain aur staged work waste karte hain.

Latency vs throughput — kya fark hai?

Latency = ek op ko khatam hone mein time; throughput = per cycle kitne ops start hote hain.

ROB kya provide karta hai aur uska size kyun matter karta hai?

Out-of-order execution ke bawajood in-order commit (precise exceptions); bada ROB independent kaam dhundhne ke liye wider window deta hai, IPC raise karta hai.