Hazard detection units

5.2.10 · Hardware › Processor Datapath & Pipelining

Yeh Kaunsa Problem Solve Karta Hai?

Ek pipelined processor mein, multiple instructions alag-alag stages (IF, ID, EX, MEM, WB) mein ek saath execute hoti hain. Lekin kya hoga agar instruction 2 ko instruction 1 ka result chahiye pehle se, jab instruction 1 ne woh likha bhi nahi? Ya agar ek branch PC ko change kar de jab pipeline already galat instructions fetch kar chuki ho?

Hazard detection unit dedicated combinational logic hai jo:

1. Pipeline registers ko dependencies ke liye monitor karta hai
2. Control signals generate karta hai (stall, flush, forward)
3. Forwarding unit ke saath coordinate karta hai hazards resolve karne ke liye

Combinational kyun? Decisions ek single clock cycle ke andar hone chahiye—next clock edge se pehle jo galat values commit kare.

Detect Hone Wale Hazards ke Types

Architecture: Data Hazard Detection Logic

Detection Combinational Circuit

Hazard detection unit ID stage mein hota hai aur yeh dekhta hai:

• ID/EX register: Woh instruction jo abhi EX mein hai
• EX/MEM register: Woh instruction jo abhi MEM mein hai
• MEM/WB register: Woh instruction jo abhi WB mein hai
• IF/ID register: Woh instruction jo abhi ID mein hai

ID stage kyun? Yahi par hum instruction ko decode karte hain aur jaante hain ki woh kaunse registers read karta hai. Hum dependencies pehle se detect kar sakte hain, EX ke stale data use karne se pehle.

Yeh kyun matter karta hai: Baaki data hazards forwarding se resolve ho sakte hain (forwarding unit unhe handle karta hai). Hazard detection unit sirf stall karta hai jab forwarding impossible ho.

Stall Signal Generation

Jab upar wali condition true ho, hazard unit yeh assert karta hai:

• PCWrite = 0: PC ko freeze karo (next instruction fetch mat karo)
• IF/ID_Write = 0: IF/ID register ko freeze karo (current instruction ko ID mein rakho)
• Control_Mux = 0: ID/EX mein ek NOP (bubble) insert karo saare control signals zero karke

Yeh teen signals kyun?

1. PCWrite=0: Agar hum next instruction fetch karein, toh jab hum finally aage badhenge toh woh kho jaayegi
2. IF/ID_Write=0: Dependent instruction ko ID mein rokke rakho taaki woh next cycle mein sahi data ke saath retry kare
3. Control_Mux=0: Woh instruction jo ID→EX mein jaane wali thi, usse bubble (no operation) banana zaroori hai taaki woh pipeline corrupt na kare

Architecture: Control Hazard Detection

Branch Resolution aur Flushing

Branches ke liye, hazard detection unit ko:

1. Branch ko jaldi detect karna hoga (ideally ID mein registers compare karke)
2. Wrong-path instructions flush karni hongi agar branch liya gaya
3. Optionally predict karna hoga (simple version: assume not-taken)

Optimization: ID mein jaldi branch resolution

• ID stage mein comparison hardware add karo (EX mein ALU ka wait karne ki jagah)
• ID mein ek adder se branch target compute karo
• Branch penalty 3 cycles se ghatke 1 cycle ho jaati hai

Forwarding Unit ke Saath Interaction

Hazard detection unit aur forwarding unit alag hain lekin coordinate karte hain:

Alag kyun?

• Forwarding data routing ke baare mein hai (mux selection)
• Hazard detection control flow ke baare mein hai (stall/flush signals)

Implementation Details

Simplified Verilog Sketch

module hazard_detection_unit(
    input [4:0] IF_ID_Rs, IF_ID_Rt,
    input [4:0] ID_EX_Rd,
    input ID_EX_MemRead,
    output reg Stall
);
    always @(*) begin
        // Load-use detection
        if (ID_EX_MemRead && 
            ((ID_EX_Rd == IF_ID_Rs) || (ID_EX_Rd == IF_ID_Rt))) begin
            Stall = 1;  // Assert stall signals
        end else begin
            Stall = 0;
        end
    end
endmodule

Yeh kyun kaam karta hai:

• Combinational (always @(*)) toh output turant update hota hai
• One-cycle delay case check karta hai jahan load EX mein hai aur dependent instruction ID mein
• Real implementations mein Rd != 0 bhi check hota hai (MIPS mein register 0 hardwired to zero hota hai)

Advanced: Multiple Hazards Handle Karna

Kya hoga agar multiple hazards ek hi cycle mein hon?

Priority rules:

1. Load-use hazard (stall) pehle aata hai—pehle resolve hona chahiye
2. Branch hazard (flush) stall complete hone ke baad apply hota hai
3. Forwarding stall ke baad hota hai, ab available data use karke

Connections

• 5.2.8-Pipeline-registers: Instructions aur control signals ko stages ke beech hold karta hai
• 5.2.9-Forwarding-unit: Zyaadatar data hazards stalling ke bina resolve karta hai
• 5.2.11-Branch-prediction: Control hazard penalties kam karta hai (advanced topic)
• 5.2.7-Pipeline-control-signals: Woh signals (RegWrite, MemRead, etc.) jo hazard detection examine karta hai
• 5.1.3-Control-unit: Original control signals generate karta hai; hazard unit unhe override kar sakta hai (mux to NOP)

#flashcards/hardware

Ek pipelined processor mein hazard detection unit kya karta hai? :: Yeh pipeline registers ko data/control dependencies ke liye monitor karta hai aur stall ya flush signals generate karta hai taaki hazards results corrupt na karein. Yeh forwarding unit ke saath coordinate karta hai hazards jahan ho sake resolve karne ke liye.

Concept Map