Memory bandwidth and latency metrics — Hinglish notes

4.1.14 · Hardware › Memory Technologies

KYA measure kar rahe hain hum?

KAISE derive karein bandwidth first principles se

Hum chahte hain: bytes moved per second. Ise build karo jo physically har clock pe hota hai usse.

Step 1 — ek transfer. Har transfer bus width $W$ bytes move karta hai. Ye step kyun? Bus $W \times 8$ wires hai; saare bits ek saath flip karte hain, isliye $W$ bytes har transfer mein cross karte hain.

Step 2 — transfers per second. Bus frequency $f$ (Hz = transfers/s for SDR) par tick karta hai. Kyun? Ek transfer per clock edge.

Step 3 — double data rate (DDR). DDR dono rising aur falling edges par transfer karta hai → factor of $2$ . Kyun? Har clock cycle mein do edges hote hain, isliye effective transfer rate $= 2 f$ .

Step 4 — parallel channels. $N$ independent channels ek saath $W$ bytes move karte hain. Kyun? Channels alag physical buses hain jo simultaneously kaam karte hain → ye add hote hain.

Combine karke:

KAISE derive karein true (CAS) latency nanoseconds mein

RAM latency CL (CAS Latency) ke roop mein clock cycles mein quote ki jaati hai, lekin frequency badhne par cycle length kam ho jaati hai. Fairly compare karne ke liye, time mein convert karo.

Step 1 — cycle time. Ek clock cycle $T_{clk} = 1/ f_{clk}$ seconds tak chalta hai. Kyun? Frequency aur period reciprocals hain.

Step 2 — DDR naming trick. DDR "data rate" = $2 f_{clk}$ . Isliye actual clock advertised MT/s number ka half hota hai.

Figure — Memory bandwidth and latency metrics

Worked examples

Forecast-then-Verify prompt

Answers padhne se pehle: Predict karo — agar 2 channels se 4 channels upgrade karo, toh (a) peak bandwidth aur (b) CAS latency ka kya hoga?

Recall Verify karo

(a) Bandwidth double ho jaata hai (channels multiply karte hain). (b) Latency unchanged rehti hai — ye per-request physical access hai, $N$ se independent.

Flashcards

Memory latency kya hai (units ke saath)?

Request issue karne se pehla byte milne tak ka time; ns ya clock cycles mein measure hota hai.

Memory bandwidth kya hai (units ke saath)?

Sustained data transfer rate, bytes/s (GB/s) mein measure hoti hai.

Bandwidth aur latency orthogonal kyun hain?

Bandwidth bus width/frequency/channels ke saath scale hoti hai; latency physical DRAM access sequence se set hoti hai, jo barely improve hoti hai.

Peak bandwidth formula?

BW = W × (2f) × N = width × data-rate × channels.

DDR mein factor of 2 kyun?

Data rising aur falling dono clock edges par transfer hota hai.

CL cycles ko nanoseconds mein convert karo?

t = CL / f_clk = 2·CL / (data-rate in MT/s) × 1000 ns.

CL16@3200 aur CL18@3600 ki equal real latency kyun ho sakti hai?

Higher frequency har cycle ko chhota kar deti hai, extra cycle ko offset karti hai.

DDR4-3200, 64-bit, dual-channel peak BW?

8 B × 3.2e9 × 2 = 51.2 GB/s.

Memory ke liye Little's Law?

Bus saturate karne ke liye outstanding bytes chahiye = Bandwidth × Latency.

Channels add karne se latency change hoti hai?

Nahi — sirf bandwidth badhti hai; per-request latency unchanged rehti hai.

Recall Feynman: ek 12-saal ke bachche ko samjhao

Socho ek paani ka pipe tank se tumhare cup tak. Latency = tap kholne ke kitni der baad pehli boond cup mein pahunchti hai — chahe pipe moti ho, agar tank door hai toh delay toh hogi hi. Bandwidth = paani chalne ke baad har second kitne liters behte hain — moti pipe zyada paani daalta hai. Zyada pipes (channels) add karne se har second zyada paani aata hai lekin pehli boond utna hi time leti hai. Isliye fast RAM "bada" (bandwidth) lag sakta hai phir bhi "wait" karwata hai (latency).

Connections

DRAM organization row buffer — physical access latency yahan se aati hai.
Cache hierarchy — caches main-memory latency hide karne ke liye exist karte hain.
DDR SDRAM generations — DDR3/4/5 transfer rate double karta hai, latency nahi.
Littles Law — throughput, latency, aur concurrency ko link karta hai.
Memory channels and interleaving — $N$ bandwidth kaise scale karta hai.
CPU memory wall — badhta hua gap: bandwidth latency se zyada fast improve hoti hai.