Combinational logic in HDL — Hinglish notes

3.5.2 · Hardware › HDL & Digital Design Flow

Combinational logic KYA hai?

Contrast karo sequential logic se, jo past inputs yaad rakhta hai (flip-flops, latches, clocks). Combinational HDL likhne ki puri kala yahi hai: function ko completely describe karo, taki tool ko kabhi kuch "yaad" na rakhna pade.

HDL style kyun matter karta hai? (Latch trap)

Synthesis tools tumhari behavioral description padhte hain aur hardware infer karte hain. Agar tumhara code kabhi bhi kehta hai "kisi case mein, purani value rakho," to tool ko memory insert karni padti hai — ek latch. Combinational block mein yeh almost kabhi nahi chahiye hota.

Kaise likhein — teen idioms

1. Continuous assignment (`assign`) — Verilog

assign y = (a & b) | ~c;

Kyun yeh combinational hai: ek assign ek permanent equation hai jo jab bhi koi right-hand-side signal change hoti hai tab re-evaluate hoti hai. y ko undriven chodne ka koi tarika nahi hai.

2. Procedural `always @(*)` block — Verilog

always @(*) begin        // sensitivity = ALL read signals
    case (sel)
        2'b00: y = a;
        2'b01: y = b;
        2'b10: y = c;
        default: y = d;  // ← the default that saves you
    endcase
end

Kyun @(*): * automatically har read signal se sensitivity list banata hai. Manual list mein koi signal miss karo aur simulation ≠ hardware ho jaata hai.
Kyun default: yeh guarantee karta hai ki y har path par assign hoga ⇒ koi latch nahi.

3. VHDL equivalent

process(all)  -- VHDL-2008 "all" = the (*)
begin
    case sel is
        when "00" => y <= a;
        when "01" => y <= b;
        when others => y <= c;  -- covers all remaining
    end case;
end process;

Blocking vs non-blocking (#1 confusion)

Kyun: blocking = immediately aur order mein execute hota hai, mimicking karta hai ki signals usi instant mein gates se kaise ripple karte hain. Non-blocking <= updates ko timestep ke end ke liye schedule karta hai, mimicking karta hai flip-flops ko jo sab clock edge par saath update hote hain.

Worked example Ripple within one block

always @(*) begin
    t = a & b;   // computed first
    y = t | c;   // uses the NEW t  ← blocking gives gate-like flow
end

Yeh step kyun? = ke saath, t update hota hai pehle y use kare — exactly jaise do chained gates. <= ke saath, y purana t padhta, intended logic tod deta.

Worked example 1 — 2-to-1 MUX (truth table se derive karo)

Truth table:

sel	y
0	a
1	b

Step 1 — Boolean function. $y = (\overline{se l} \cdot a) + (se l \cdot b)$ . Yeh step kyun? Combinational logic ek Boolean function hai; code likhne se pehle function likho.

Step 2 — Teen tarike se code karo.

assign y = sel ? b : a;              // idiom 1

always @(*) y = sel ? b : a;         // idiom 2, single line auto-complete

Yeh step kyun? Dono sel=0 aur sel=1 ke liye y ko fully specify karte hain ⇒ combinational, koi latch nahi.

Worked example 2 — ek latch bug ko steel-man karna

always @(*) begin
    if (enable)
        y = data;        // ← what if enable == 0 ??
end

Galat code sahi kyun lagta hai: "y ki mujhe tabhi parwah hai jab enable high ho." Efficient lagta hai — else kyun likhein?

Actually kya hota hai: jab enable==0, y assign nahi hota, to tool ko purani value hold karni padti hai ⇒ woh transparent latch infer karta hai. Ab y mein woh memory hai jo tumne kabhi socha nahi tha — timing hazards, design close karna mushkil.

Common mistake Latch ki galti

Fix: if se pehle ek default assign karo, ya else add karo.

always @(*) begin
    y = 1'b0;          // default covers every path
    if (enable) y = data;
end

Ab enable==0 ⇒ y=0 (defined) ⇒ pure combinational.

Worked example 3 — full adder first principles se

Step 1 — Truth table → equations. Sum tab 1 hota hai jab odd number of inputs 1 hon; carry tab jab ≥2 inputs 1 hon: $s = a \oplus b \oplus c_{in}, c_{o u t} = (a \cdot b) + (c_{in} \cdot (a \oplus b))$ Yeh step kyun? 1s count karne se derive karo — koi memorization nahi.

Step 2 — HDL:

assign s    = a ^ b ^ cin;
assign cout = (a & b) | (cin & (a ^ b));

Yeh step kyun? Do continuous assigns ⇒ har output permanently driven ⇒ guaranteed combinational.

Recall Feynman: 12-saal ke bacche ko samjhao

Socho ek vending machine jisme koi memory nahi hai. Tum buttons dabate ho (inputs) aur turant ek snack girta hai (output) sirf usi cheez ke basis par jo tumne abhi dabaya — use tumhari pichli visit yaad nahi rehti. Combinational logic wahi machine hai. Catch yeh hai: agar tum machine ko kisi situation mein kya karna hai yeh batana bhool jaate ho, toh woh confuse ho jaati hai aur hamesha "last snack yaad rakhne" lagti hai — woh accidental memory latch kehlati hai, aur yeh ek bug hai. Isliye tumhe har button combination ke liye rule dena hoga.

Active recall

Combinational logic kis cheez par depend karta hai?

Sirf present inputs par — koi memory nahi, koi clock nahi, koi feedback state nahi.

Combinational block mein ek unassigned output kaun sa hardware infer karta hai?

Ek transparent latch (unintended memory).

Manual sensitivity list ki jagah always @(*) kyun use karte hain?

* automatically har read signal ko include karta hai, simulation-vs-synthesis mismatch rok ke.

Combinational always block mein blocking (=) ya non-blocking (<=)?

Blocking =, kyunki yeh order mein execute hota hai jaise signals gates se ripple karte hain.

always @(*) mein latch inference rokne ke do tarike?

Branches se pehle ek default value assign karo, aur/ya ek default/else daalo jo saare paths cover kare.

Full adder ka sum equation likho.

s = a \oplus b \oplus c_{in}

Full adder ka carry-out likho.

c_{o u t} = (a \cdot b) + (c_{in} \cdot (a \oplus b))

Continuous assign hamesha combinational kyun hota hai?

Yeh ek permanent equation hai jo kisi bhi input change par re-evaluate hoti hai; output kabhi undriven nahi reh sakta.

Connections

Sequential logic in HDL — woh counterpart jo actually state rakhta hai (flip-flops, clocks).
Latch inference and how to avoid it
Blocking vs Non-blocking assignments
Boolean algebra and Karnaugh maps — jahan se functions aate hain.
Synthesis and the digital design flow
Multiplexers, adders, decoders — canonical combinational building blocks.