5.5.25 · D4 · HinglishEmbedded Systems & Real-Time Software

ExercisesRedundancy — TMR (triple modular redundancy), voting logic

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5.5.25 · D4 · Coding › Embedded Systems & Real-Time Software › Redundancy — TMR (triple modular redundancy), voting logic

Yeh page ek self-testing ladder hai. Har problem clearly diya gaya hai, phir ek collapsible Solution callout ke peeche chhupa hua hai — pehle khud try karo, tab reveal karo. Hum recognising se shuru karte hain ki TMR kya hai (L1), aur mastering tak jaate hain — reliability trade-offs aur voter design (L5). Yahan sab kuch parent TMR note pe based hai — agar koi symbol unfamiliar lage, woh wahan define kiya gaya tha, aur hum use neeche re-anchor karte hain jab zarurat ho.

Do symbols jo shuru karne se pehle clearly yaad hone chahiye:

Woh master formula jis par hum baar baar lean karte hain:


Level 1 — Recognition

Exercise 1.1

Teen modules binary values , , output karte hain. Majority voter kya output karega?

Recall Solution

Hum kya karte hain: count karo ki teen outputs mein kitne hain. Do ones () aur ek zero. Majority voter woh value return karta hai jo kam se kam do inputs share karte hain. Do par agree karte hain, isliye output hai. ka akela mask ho jaata hai — system se chhup jaata hai.

Exercise 1.2

Ek single module ki reliability hai. Bina kisi formula ke, kya teen aise modules se bana TMR system ek module se zyada ya kam reliable hoga? Ek-line ka reason do.

Recall Solution

Zyada reliable. Kyunki hai, har module ke fail hone se zyada chances hain ki woh kaam kare, isliye do ka ek saath fail hona rare hai. Voter ko sirf do good modules chahiye, toh woh almost always correct majority dekhta hai. (Number L2 mein prove karte hain.)

Exercise 1.3

Inme se TMR kya kar sakta hai? (a) ek faulty module ko mask karna, (b) batana ki kaun sa module fail hua, (c) do simultaneous faulty modules tolerate karna.

Recall Solution

Sirf (a).

  • (b) galat hai: TMR faults ko mask karta hai, diagnose nahi karta — tum jaante ho ki koi disagree kar raha hai, par kaun nahi (uske liye Watchdog Timers ya self-checking pairs add karo).
  • (c) galat hai: agar teen mein se do kharab ho jaayein, toh woh ek sahi module ko outvote kar sakte hain. TMR exactly ek faulty module tolerate karta hai.

Level 2 — Application

Exercise 2.1

Har module ki hai. use karke compute karo.

Recall Solution

Hum kya karte hain: ko master formula mein substitute karo. Kyun matter karta hai: failure probability (single) se gir kar (TMR) ho gayi — improvement, hardware ke cost par.

Exercise 2.2

Har module ki hai. TMR failure probability kya hai?

Recall Solution

, aur . Kyun yeh headline number hai: ek single module probability se fail hota hai; TMR probability se fail hota hai — lagbhag safer. Jitne better base modules, utna dramatically TMR pay off karta hai, kyunki two-out-of-three simultaneous failures astronomically rare ho jaate hain.

Exercise 2.3

Teen temperature sensors , , read karte hain. Exact majority voting apply karo. Output kya hai, aur kaun si reading mask hoti hai?

Recall Solution

Hum kya karte hain: do equal readings dhundho. . Do par agree karte hain, isliye output . reading mask ho jaati hai — yeh outlier hai (likely ek calibration/bias fault). System trusted majority value ke saath aage badhta hai.


Level 3 — Analysis

Exercise 3.1

Har module ki hai. compute karo aur single module se compare karo. Difference ka sign explain karo.

Recall Solution

, . Single module reliability hai. Kyunki hai, TMR worse hai. Kyun: jab hota hai, har module kaam karne se zyada fail karta hai, isliye do modules ka saath fail hona common hai aur woh ek sahi module ko outvote kar dete hain. Redundancy unreliability ko cure karne ki jagah amplify kar deti hai. Neeche wala figure is crossover ko visually dikhata hai.

Neeche wala figure padhna. Horizontal axis single-module reliability hai ( se tak); vertical axis resulting system reliability hai. Violet straight line woh hai jo ek module se milti hai (baseline — system reliability sirf module reliability ke barabar hai). Magenta curve TMR hai. Dono lines orange dashed line par (black dot par) cross karti hain. Us dashed line ke daayein magenta curve violet line ke upar hoti hai — TMR jeet jaata hai (shaded region "TMR helps"); baayein magenta violet ke neeche dip karti hai — TMR haar jaata hai (shaded "TMR hurts"). Violet square hamare worked point ko mark karta hai, jo comfortably winning region mein hai; is exercise ka losing region mein hai.

Figure — Redundancy — TMR (triple modular redundancy), voting logic

Exercise 3.2

ki woh value dhundo jahan ho (woh "crossover" reliability jahan TMR na help karta hai na hurt, trivial endpoints aur ke alaawa).

Recall Solution

Hum kya karte hain: set karo aur solve karo. Quadratic factor karo: . Interpretation: interesting crossover hai — exactly woh orange dashed line jo upar figure mein hai. Isse upar TMR help karta hai (); neeche TMR hurt karta hai. Yeh parent note ka critical-threshold claim hai, ab assert karne ki jagah derived kiya gaya hai.

Exercise 3.3

Teen analog outputs hain , , . Average voter aur median voter compare karo. Kaun fault mask karta hai?

Recall Solution

Pehle, key idea: quantitative (real-valued) outputs ke liye, median majority voting ka direct generalization hai. Binary majority woh value pick karta hai jo "zyada" modules share karte hain; jab values continuous hain aur rarely exactly match karte hain, median middle value pick karta hai, jo by construction us cluster ke saath hoti hai jahan kam se kam do modules land kiye — wahi "majority par trust karo, lone dissenter discard karo" logic, bas exact equality ki jagah position se measure kiya gaya.

Average: (2 dp tak). Wild answer ko do sane readings se door kheench leta hai. Median: sort karo, middle lo . Outlier completely ignore ho jaata hai. Kyun median jeetta hai: median sirf ordering care karta hai, magnitude nahi, isliye ek single arbitrarily large fault use ek position se aage nahi hila sakta. Average ek sum hai, isliye ek bada value use poison kar deta hai. Fault masking ke liye median use karo.


Level 4 — Synthesis

Exercise 4.1

Binary inputs ke liye Boolean majority gate design karo. Expression likho, phir input row par verify karo.

Recall Solution

Hum kya karte hain: output hoga iff kam se kam do inputs hain. Har pair ka par agree karna ek AND term hai; "any pair" OR hai: par verify karo: Sahi — do ones present hain, isliye majority hai. (Yahan logical OR hai aur juxtaposition AND hai.)

Exercise 4.2

Voter khud ek physical component hai jiska reliability hai. Teen modules mein se har ek ki hai. Yeh assume karte hue ki system tab hi kaam karta hai jab (module majority hold ho aur voter kaam kare), poori system reliability likho aur evaluate karo.

Recall Solution

Hum kya karte hain: do independent cheezein hain jo dono succeed honi chahiye — modules ki majority, aur voter. Independent successes multiply hote hain. Kyun yeh matter karta hai: voter ek single point of failure hai — agar woh mar jaaye, toh saari module redundancy bekaar hai. Yahi reason hai ki real TMR voters hardened hote hain ya khud triplicated hote hain. Notice karo : voter sirf reliability subtract kar sakta hai.

Exercise 4.3

Tumhare paas wale modules hain. Kya tum prefer karoge (a) teen se TMR build karna, ya (b) utni hi effort mein ek module ko tak pahunchana? Justify numerically.

Recall Solution

TMR path: . Better-single path: by assumption. Kyunki hai, pure reliability par better single module jeet ta hai — aur ki jagah hardware aur power use karta hai. Nuance: TMR phir bhi transient faults (cosmic-ray bit-flips) ke against tolerance deta hai jo ek module improve karke nahi mil sakti, kyunki tum ek random future event ko design out nahi kar sakte. Isliye honest answer hai: pehle base reliability fix karo (parent-note advice), phir remaining transient risk ke liye TMR add karo jo tum design away nahi kar sakte.


Level 5 — Mastery

Exercise 5.1

Teen modules mein se do mein ek hidden common-cause defect hai: probability ke saath woh dono saath fail ho jaate hain (ek single correlated event aur dono ko ek saath knock out kar deta hai). Arithmetic clean rakhne ke liye, hum modelling assumptions explicit karte hain: us shared event ke alaawa, aur ki negligible independent failure probability hai, aur independently probability se fail hota hai. In stated assumptions ke under, estimate karo ki system apni majority khone ki probability kya hai.

Recall Solution

Pehle model state karo (yahi exercise ka point hai):

  • Common-cause event , ke saath fire hota hai aur dono aur ko kill kar deta hai.
  • By assumption ka koi aur failure route nahi hai, isliye agar fire nahi karta, toh dono healthy hain.
  • independently se fail hota hai.

Hum kya karte hain: majority tab lose hoti hai jab do ya zyada modules fail ho jaayein.

  • Agar fire karta hai (prob ): aur dono down hain → do failures → majority already lost, chahe kuch bhi kare.
  • Agar fire nahi karta (prob ): hamare stated assumption ke under healthy hain, isliye zyada se zyada down hai — sirf ek failure → majority survive karta hai.

Isliye majority tab lost hoti hai iff fire karta hai: Lesson: ek common-cause coupling completely design ko dominate kar deta hai — yeh akele hi reliability ko par cap kar deta hai, chahe independent failure rate kitna bhi achha ho (agar hum ke liye small independent failures include karte, toh answer se sirf thoda upar hota, isliye conclusion robust hai). Yahi reason hai ki Common-Cause Failures aur Redundancy vs. Diversity matter karte hain: identical triplicated modules identical flaws share karte hain. Real safety systems correlation break karne ke liye diverse implementations use karte hain.

Exercise 5.2

Per-module ke saath TMR aur 5-modular redundancy (5MR) compare karo. 5MR survive karta hai agar mein se kam se kam modules work karein. compute karo aur qualitative gain state karo.

Recall Solution

Hum kya karte hain: mein se "3 work", "4 work", "5 work" ke binomial probabilities sum karo, , ke saath. Yaad karo . Toh 5MR failure probability se tak push karta hai — roughly safer, hardware aur ek voter ke cost par jo do faults tolerate karta hai instead of one. Diminishing returns: hardware 3 se 5 tak double karne se safety margin double nahi hua.

Exercise 5.3

Ek mission ko system failure probability se kam chahiye. Tumhare modules ki hai. Kya plain TMR requirement meet karta hai? Agar haan, toh kitne margin se; agar nahi, toh tum kya change karoge?

Recall Solution

Exercise 2.2 se, hai, isliye Requirement hai. Kyunki hai, plain TMR meet nahi karta — roughly se miss karta hai. Kya change karna hai (leverage ke order mein):

  1. Base badhao: thodi si bhi improvement effect mein cube-ish hoti hai. try karo: , failure — easily pass karta hai.
  2. Agar modules improve nahi kar sakte, toh 5MR use karo (Ex. 5.2 style).
  3. Mat bhulo voter aur common-cause terms — woh, Ex. 4.2 aur 5.1 ke according, dominate kar sakte hain aur silently budget blow kar sakte hain. Safety-Critical Systems Standards ke against certify karne se pehle hamesha unhe fold in karo.

Recall Quick self-quiz (finish karne ke baad reveal karo)

TMR crossover reliability jiske neeche redundancy hurt karta hai ::: Majority-gate Boolean expression ::: Kyun median analog voter ke roop mein average se better hai ::: median gross outliers ignore karta hai; average unse poison ho jaata hai TMR mein single point of failure kaun sa component hai ::: voter Module count chahe kitna bhi ho, reliability ko kya cap karta hai ::: common-cause (correlated) failures