Exercises — Software testing in embedded — unit tests on host, HIL testing

• (a) HOST — ek array par pure arithmetic, koi peripheral nahi. ✅
• (b) HIL — latency ek event aur interrupt service routine (ISR) ke run hone ke beech ka real time elapsed hai; host time ko mock karta hai isliye ise measure nahi kar sakta.
• (c) HOST — booleans in, enum out, koi hardware nahi.
• (d) HIL — noise real analog-to-digital converter ki ek electrical property hai; ek mock exactly wo number return karta hai jo tumne inject kiya, isliye uska noise zero hota hai. Rule of thumb: agar tum use plain numbers ke roop mein inputs de sako aur outputs ko plain numbers ke roop mein check kar sako, to wo host-testable hai.

Line A — ADC1->DR ek physical hardware register read karta hai jo tumhare PC par exist hi nahi karta, isliye program host par crash karta hai (ya link bhi nahi hota). Fix using a HAL seam:

uint16_t v = hal_adc_read(ADC_CHANNEL_1);

Ab ek mock host par v supply kar sakta hai. Line B (process) pehle se hi pure logic thi aur isme koi change ki zaroorat nahi.

Logic lines $=1000-120-80=800$. Poori file ka fraction jo logic hai: $\frac{800}{1000}=0.80=80\%.$ Toh file ka 80% woh logic hai jise tumhe hard test karna chahiye; baaki 20% (driver + glue) ya to vendor-tested hai ya trivially thin. Agar tum saari 800 logic lines cover karo tum coverage bar comfortably hit karte ho. Target meet hota hai. ✅

Max ADC code $=2^{12}-1=4095$ (yeh full-scale voltage $3.3\text{ V}$ represent karta hai). Conversion linear hai — code voltage ke proportional hai: $\text{code}=\lfloor \frac{V_{\text{in}}}{V_{\text{ref}}}\times 4095\rfloor =\lfloor \frac{1.65}{3.3}\times 4095\rfloor .$ $\frac{1.65}{3.3}=0.5$, toh $0.5\times 4095=2047.5$, floor $=2047$. (Full scale ka half code 2047 hai, geometric midpoint se ek neeche kyunki hum 0 se count karte hain.)

Linear map: $\text{pwm}=\lfloor \frac{\text{code}}{4095}\times 1000\rfloor$, phir clamp to $[0,1000]$.

• code $4095$: $\lfloor 1000\rfloor =1000$ → exactly cap hit hota hai. Parent note ke assert(... == 1000) se match karta hai.
• code $2047$: $\lfloor \frac{2047}{4095}\times 1000\rfloor =\lfloor \mathrm{499.87...}\rfloor =499$.

Latency = response time − trigger time: $T_{\text{measured}}=12.563-12.480=0.083\text{ms}=83\mu \text{s}.$ Compare: $83\mu \text{s}<100\mu \text{s}$ → PASS (margin $17\mu \text{s}$). Host kyun nahi pakad sakta: host par, time mocked hota hai — ISR tumhare test harness dwara ek plain function ki tarah call kiya jaata hai, toh "hardware use kab tak run karega" ka koi matlab nahi hota. Real ISR latency CPU clock, higher-priority interrupts, aur cache/pipeline effects par depend karti hai jo sirf real target par exist karte hain.

New response time = old + added blocking cost: $6.2+5.0=11.2\text{ms}.$ Deadline $10\text{ms}$ hai, aur $11.2>10$ → FAIL. Old margin tha $10-6.2=3.8\text{ms}$ (slack, green in the figure). New margin hai $10-11.2=-1.2\text{ms}$ (overrun, red). Margin exactly utna shrink hua jitna $5.0\text{ms}$ humne add kiya. Yeh ek timing regression hai — HIL isi ko pakadne ke liye exist karta hai.

Host total: $40\times 3\text{ms}=120\text{ms}=0.12\text{s}$. HIL total: $8\times 4\text{s}=32\text{s}$. Ratio HIL : host $=32/0.12\approx 267$. HIL yahan ~267× slower hai. Har logic bug jo tum host par pakad sako ek ~267×-zyada-expensive round trip bachata hai — yahi two-tier strategy ka poora argument hai.

Seams (mock/stub karo):

• hal_adc_read(ADC_TEMP) — ek stub jise tum set karo; injected value return karta hai.
• hal_led_set(FAULT_LED, on) — ek mock jo last state record karta hai (spy), taaki test ise read back kar sake. Refactored:

void safety_check(void) {
    bool over = hal_adc_read(ADC_TEMP) > 3000;
    hal_led_set(FAULT_LED, over);
}

Boundary: branch code $3000$ (LED off, > false hai) aur $3001$ (LED on) ke beech flip hoti hai. Toh separating boundary 3000 aur 3001 ke beech hai. Do tests (dono branches + boundary cover karo):

// branch 1: below/at threshold -> LED off
mock_set_adc(ADC_TEMP, 3000); safety_check(); assert(mock_led == 0);
// branch 2: above threshold -> LED on
mock_set_adc(ADC_TEMP, 3001); safety_check(); assert(mock_led == 1);

3000 aur 3001 choose karna (0 aur 4095 nahi) decision ko test karta hai, jahan bugs rehte hain.

Host tests har commit ko gate karte hain kyunki yeh ~saikdon guna faster hain (Ex 3.3) aur debuggable hain; HIL nightly shared rig par run hota hai kyunki yeh slow aur hardware-limited hai.

(a) Response time do edges ka delta hai: $t_1-t_0=48.500-40.000=8.500\text{ms}.$ (b) $8.5\text{ms}<10\text{ms}$ → PASS, margin $=10-8.5=1.5\text{ms}$. (c) Stuck-high ADC → DUT sochta hai throttle hamesha max code 4095 par hai → compute_pwm cap 1000 tenths = 100% duty return karta hai (Ex 2.3 se). Yeh kabhi 5% se neeche nahi girta, toh while(pwm > 5.0) loop hamesha spin karta rahta hai → test time out / fail hota hai — jo sahi result hai: firmware ke paas frozen sensor detect karne ka koi independent tarika nahi hai. Insight: host tests control math verify karte hain; plain HIL real hardware par timing verify karta hai; HIL + fault injection broken hardware ke under safety behaviour verify karta hai. Sirf combination yeh expose karta hai ki ek stuck sensor motor ko full power par drive karta hai — teeno mein se sabse dangerous, sabse real-world failure.

(a) Cover karne wali lines $=0.80\times 800=640$. Tests needed $=\lceil 640/12\rceil =\lceil 53.33\rceil =54$ host tests. (b) Host time $=54\times 3\text{ms}=162\text{ms}=0.162\text{s}$. (c) HIL time $=3\times 4\text{s}=12\text{s}$. Total $=0.162+12=12.162\text{s}$. (d) Gate sirf host tier run karta hai: $0.162\text{s}<2\text{s}$ budget → sane, gate on host. HIL ke 12 s nightly run hote hain, per-commit nahi. Yeh exactly Ex 4.2 wala two-tier split hai, ab quantified.

12-bit ADC ka full-scale code ::: 4095 (yani $2^{12}-1$, 0 se count karte hue) Host tests ISR latency kyun measure nahi kar sakte ::: host time ko mock karta hai, isliye real elapsed duration ka koi matlab nahi; sirf real hardware ke paas real clock hota hai Do logic-analyzer timestamps se latency ::: response edge minus trigger edge (ek difference, kabhi single stamp nahi) Kaunsa tier har commit gate karta hai aur kyun ::: host unit tests — saikdon guna faster aur debug karna easy Threshold boundary tests kahan place karo ::: threshold ke theek neeche aur theek upar, extremes par nahi