5.5.8
Socho tum ek manager (CPU ) ho aur boxes ka ek truck (data) loading dock (ek peripheral) se warehouse shelves (memory) mein move karna hai. Tum khud har ek box uthaa ke le ja sakte ho, ek-ek karke — lekin tab tum kuch aur nahi kar sakte. Isliye tum ek dedicated mover (DMA controller ) hire karte ho jo boxes directly copy karta hai jabki tum real kaam karne jaate ho. Wahi mover hai DMA: Direct Memory Access — ek hardware engine jo bytes ko addresses ke beech CPU ko touch kiye bina shuffle karta hai.
DMA (Direct Memory Access) ek hardware controller hai jo do memory regions ke beech, ya ek peripheral aur memory ke beech, data transfers perform karta hai — CPU se independent hokar . CPU sirf transfer program karta hai (source, destination, count, mode) aur phir DMA engine har word move karta hai, kaam hone par ek interrupt signal karke.
Teeno canonical transfer directions:
Direction
Source
Destination
Typical use
Mem-to-Mem RAM
RAM
memcpy acceleration, framebuffer copy
Periph-to-Mem UART/ADC/SPI data register
RAM buffer
sensor samples logging karna
Mem-to-Periph RAM buffer
DAC/SPI/UART data register
audio streaming out
Intuition Why not just let the CPU copy?CPU ka for loop jo N load → store execute karta hai har word ke liye, plus loop overhead, aur iske dauran woh kuch aur nahi kar sakta. 1 MB framebuffer ke liye yeh millions of cycles sirf plumbing pe waste hote hain. DMA wahi load/store dedicated silicon mein karta hai, CPU ko compute ke liye free karta hai. Yeh fast peripheral data ka deterministic, low-latency capture bhi enable karta hai jo CPU otherwise miss kar sakta hai (jaise ek ADC jo har microsecond fire karta hai).
Deeper win hai parallelism : jab DMA bus own karke data move karta hai, CPU cache/instruction memory se run karta hai.
Ek transfer completely 4 cheezein describe karti hain jo tumhe set karni hoti hain:
Source address S Destination address D Count N Item width w
Total bytes moved: B = N ⋅ w
Har DMA "beat" ek item move karta hai aur kuch bus cycles consume karta hai. Maano:
f c
Time per beat:
t beat = f c
Total transfer time (setup ignore karke):
t DMA = N ⋅ t beat = f N c
Har beat mein, controller addresses update karta hai:
S i + 1 = S i + Δ S , D i + 1 = D i + Δ D
Mem-to-mem : Δ S = Δ D = w Periph-to-mem : Δ S = 0 Δ D = w Mem-to-periph : Δ S = w Δ D = 0
Intuition Peripheral address fix kyun rakhte hain?Peripheral ka data register ek single hardware address hota hai (jaise UART->DR). Naye bytes usi address par appear hote hain har baar jab peripheral ready hota hai. Toh tum ek jagah se baar baar read karte ho, lekin successive RAM slots mein scatter karte ho.
Mem-to-mem usually software-triggered hota hai: program karo, enable bit set karo, full speed chalega.Periph transfers hardware-triggered hote hain: peripheral ek DMA request line assert karta hai jab bhi uske paas ek item hota hai/chahiye (jaise "ADC conversion ready"). DMA har request par ek beat perform karta hai → naturally rate-matched.
Intuition Bus arbitration ("cycle stealing")DMA aur CPU ek memory bus share karte hain — ek waqt mein sirf ek hi drive kar sakta hai. Ek arbiter bus grant karta hai. Cycle-stealing mode mein DMA bus ko ek beat ke liye grab karta hai, phir release karta hai taaki CPU starve na ho. Burst mode mein DMA poore block ke liye bus hold karta hai (faster, lekin CPU stall ho sakta hai). Yeh ek latency vs. throughput trade-off hai.
Worked example 1 — ADC capture ka throughputEk 12-bit ADC 16-bit (2-byte) RAM slots mein store karta hai, periph-to-mem, N = 1000 f = 48 c = 1
t DMA = N c / f = 1000/48 , 000 , 000 ≈ 20.8 μ s Yeh step kyun? Har beat = 1 cycle, 1000 beats.Throughput = w f / c = 2 × 48 e6 = 96 Kyun? 2 bytes per beat × 48M beats/s.
CPU saved (k = 4 1000 × 4 = 4000 83 μ s
Worked example 2 — Array ka Mem-to-mem copy256 words copy karo (w = 4 f = 72 c = 1
B = 256 × 4 = 1024 Kyun? count × width.t = 256/72 e 6 ≈ 3.56 μ s Δ S = Δ D = 4 Kyun? mem-to-mem dono buffers aage walk karta hai.
Worked example 3 — Item width choose karna4096 bytes move karne hain. Compare karo w = 1 N = 4096 w = 4 N = 1024 f = 48 c = 1
w = 1 t = 4096/48 e 6 = 85.3 μ s w = 4 t = 1024/48 e 6 = 21.3 μ s 4× faster . Kyun? Kam, wider beats same bytes ko kam cycles mein move karte hain. Jitna widest aligned width buffers allow karein, use karo.
Common mistake "DMA instant / free hai — zero cost."Kyun sahi lagta hai: CPU busy nahi hai, toh lagta hai jaise magic hai. Fix: DMA phir bhi bus cycles aur bus bandwidth consume karta hai. Jab woh bus hold karta hai, CPU ek memory access par stall ho sakta hai (khaaskar burst mode mein). Yeh CPU ke compute pipeline ke liye free hai, memory subsystem ke liye nahi.
Common mistake "Main DMA buffer ko transfer start karte hi immediately read kar sakta hoon."Kyun sahi lagta hai: tumne start function call kiya, toh surely ho gaya hoga. Fix: DMA asynchronous hai. Data use karne se pehle tumhe transfer-complete interrupt/flag ka wait karna zaroori hai. Jaldi read karne se stale/partial bytes milte hain.
Common mistake "Cache + DMA bas kaam karta hai."Kyun sahi lagta hai: simple MCUs mein cache nahi hota, toh sach mein kaam karta hai. Fix: data cache ke saath, DMA RAM mein likhta hai lekin CPU ek cached stale value read kar sakta hai (aur vice versa). DMA input padhne se pehle cache invalidate karo, aur DMA ke CPU output padhne se pehle cache clean/flush karo. Yeh classic cache coherency bug hai.
Common mistake "Sahi address increment karna bhool jaana."Kyun sahi lagta hai: mem-to-mem dono increment karta hai, toh assume karte ho periph bhi karta hai. Fix: ek peripheral register fixed hota hai (Δ = 0
Recall Feynman: ek 12-saal ke bacche ko explain karoComputer ka dimag busy sochne mein laga hai. Ek bade pile of papers ko ek desk se doosri desk par uthana boring busy-work hai. Toh dimag ek robot helper (DMA) hire karta hai: "Desk A se papers lo, desk B par rakh do, 1000 papers, phir kaam hone par mujhe tap karo." Dimag sochta rehta hai jabki robot papers uthata rehta hai. Robot fast hai aur kabhi bore nahi hota — lekin dono ek hallway (the bus) share karte hain, toh kabhi-kabhi dimag ko robot ke guzarne ka thoda wait karna padta hai.
Koi bhi DMA set up karne ke liye "S.C.A.M." yaad rakho: S ource, C ount, A ddress-increment mode, M ode/trigger. Phir enable karo aur interrupt ka wait karo . (Aur yaad rakho: DMA ek "SCAM" hai kyunki kaam woh karta hai aur credit CPU leta hai. 😄)
DMA ka full form kya hai aur yeh kya karta hai? Direct Memory Access — ek hardware controller jo memory/peripherals ke beech data transfer karta hai bina CPU ke har word ko handle kiye.
CPU copy loop ki jagah DMA kyun use karein? CPU ko compute ke liye free karta hai (parallelism), deterministic low-latency capture deta hai, aur dedicated hardware se data kam cycles mein move karta hai.
DMA transfer time ka formula? t = N c / f
DMA throughput ka formula, aur N kyun appear nahi karta? Throughput = w f / c
Periph-to-mem mode mein source aur destination address increments kya hote hain? Source (peripheral register) Δ=0 (fixed); destination (RAM buffer) Δ=w (increment hota hai).
Transfer ke dauran peripheral address fixed kyun hota hai? Peripheral ka data register ek single hardware address hai; naye bytes har baar ready hone par usi location par appear hote hain.
Cycle stealing kya hai? DMA bus ko ek beat ke liye grab karta hai phir release karta hai, taaki CPU starve na ho — throughput ki jagah lower CPU latency ke liye trade-off.
Cached CPU par DMA-filled buffer READ karne se pehle kya karna chahiye? Data cache invalidate karo taaki CPU fresh RAM contents dekhe, stale cached values nahi.
DMA truly "free" kyun nahi hai? Yeh bus bandwidth/cycles consume karta hai; jab DMA bus hold karta hai CPU memory accesses par stall ho sakta hai.
DMA result data kab safely use kar sakte ho? Sirf tab jab transfer-complete interrupt/flag fire ho jaaye (DMA asynchronous hai).
Fixed total bytes ke liye wider item width transfer time ko kaise affect karta hai? Wider items → kam beats → proportionally faster (4-byte ≈ 4× faster than 1-byte).
Peripheral-to-memory DMA beat ko kya trigger karta hai? Peripheral ki taraf se ek hardware DMA request line assert hoti hai jab uske paas data ready hota hai (rate-matched).
Interrupts and ISRs — DMA completion ek interrupt ke through signal karta hai.Memory-Mapped IO — peripheral data registers fixed addresses hain jo DMA read/write karta hai.Cache Coherency — classic DMA stale-data trap.Bus Arbitration — CPU aur DMA ek memory bus kaise share karte hain.Circular and Double Buffering — continuous streaming ke liye DMA modes.ADC and DAC — common DMA-driven peripherals.memcpy and Block Copy — mem-to-mem DMA ise accelerate karta hai.
