Switching — circuit, packet, virtual circuit

WHAT is switching?

The whole subject splits along two questions:

Is a dedicated path reserved in advance? (resource reservation)
Does each switch keep per-connection state?

	Path reserved?	Per-connection state?	Decision time
Circuit switching	Yes (whole bandwidth)	Yes	Before data (setup)
Packet switching (datagram)	No	No	Per packet, on the fly
Virtual circuit	Logical path, not bandwidth	Yes (VC table)	Setup, then forward by label

1. Circuit Switching

HOW it works

Setup: a request propagates hop-by-hop; each switch reserves a channel (e.g., a time slot in TDM or a frequency band in FDM) and links input↔output.
Transfer: data flows with no per-hop header processing — the path is hardwired.
Teardown: resources are released.

Deriving the total delay

Let:

$S$ = setup time (signaling to build the circuit),
$d$ = number of links (hops), $t_p$ = propagation delay per link,
$L$ = message size (bits), $R$ = link rate (bits/s).

Once the circuit exists, the message streams continuously; it is not stored at each switch, so the bits flow like water in a pipe.

$T_{\text{circuit}} = \underbrace{S}_{\text{setup}} + \underbrace{d\,t_p}_{\text{propagation along path}} + \underbrace{\frac{L}{R}}_{\text{transmission of message}}$

Why this form? After setup, the first bit travels across all $d$ links (cost $d\,t_p$ ), and the source pushes all $L$ bits at rate $R$ (cost $L/R$ ). There is no store-and-forward $\Rightarrow$ no $\times d$ on the transmission term.

2. Packet Switching (Datagram)

HOW the table works: each router looks at the destination address and consults a forwarding/routing table → outgoing link. State is not per-connection; it's per-destination (global routes).

Deriving the delay (store-and-forward)

Send one message of $L$ bits split into nothing (single packet) across $d$ links, rate $R$ , propagation $t_p$ per link.

Because each switch must receive the whole packet before sending it on, each of the $d$ links costs a transmission time $L/R$ , serially:

$T_{\text{1 packet}} = d\cdot\frac{L}{R} + d\,t_p$

Why $d\cdot L/R$ ? The packet is reborn at each hop — switch 1 finishes receiving (time $L/R$ ) before pushing to switch 2, etc. This serial replay is the cost of store-and-forward.

Now the magic — pipelining with $P$ packets. Split $L$ into $P$ packets of size $L/P$ each (ignoring header). The first packet reaches the destination after $d\cdot\frac{L/P}{R}$ transmission, then the remaining $P-1$ packets stream behind it pipeline-style, one $\frac{L/P}{R}$ apart:

$T_{\text{P packets}} = \underbrace{d\cdot\frac{L/P}{R}}_{\text{first packet across}} + \underbrace{(P-1)\cdot\frac{L/P}{R}}_{\text{rest pipelined}} + d\,t_p = \frac{(d+P-1)}{P}\cdot\frac{L}{R} + d\,t_p$

Why pipelining helps: while link 2 carries packet 1, link 1 already carries packet 2. As $P$ grows, $\frac{d+P-1}{P}\to 1$ , so transmission cost $\to L/R$ — the same as if there were a single hop! Smaller packets ⇒ more pipelining ⇒ lower delay (until headers dominate).

Figure — Switching — circuit, packet, virtual circuit

3. Virtual Circuit Switching

HOW label swapping works: at each hop the switch reads the incoming VC number, looks it up, swaps it for the outgoing number from its table, and forwards. The label is locally meaningful only.

Comparison summary

Feature	Circuit	Datagram	Virtual Circuit
Setup phase	Yes (reserve BW)	No	Yes (logical only)
Bandwidth reserved	Yes	No	No
Per-packet address	none	full destination	small VC label
Path	fixed, dedicated	varies per packet	fixed, shared
Ordering guaranteed	Yes	No	Yes
State in switch	per-circuit	per-destination route	per-VC table
Header overhead	low	high	low
Wastes BW if idle	Yes	No	No

Worked example Worked: which is faster to send a 1 MB file?

$L = 8\times10^6$ bits, $R = 1$ Mbps $=10^6$ bps, $d=3$ hops, $t_p = 1$ ms, setup $S = 100$ ms. Circuit: $T = 0.1 + 3(0.001) + \frac{8\times10^6}{10^6} = 0.1 + 0.003 + 8 = 8.103$ s. Why? Transmission dominates (8 s); store-and-forward avoided so only one $L/R$ . Datagram, 1 packet: $T = 3\cdot 8 + 0.003 = 24.003$ s. Why so bad? Each hop replays all 8 Mbit serially. Datagram, 1000 packets: $T = \frac{3+999}{1000}\cdot 8 + 0.003 = 1.002\cdot8 + 0.003 = 8.019$ s. Why now competitive? Pipelining ⇒ effective transmission ≈ $L/R$ , and no 100 ms setup, so it even beats circuit. This is why the internet uses packet switching.

Recall Feynman: explain to a 12-year-old

Imagine sending toy cars to a friend across a city of crossroads. Circuit switching: you call ahead and policemen clear a whole private road just for your cars — fast and smooth, but the road sits empty while you decide which car to send, and nobody else can use it. Packet switching: you write your friend's full address on every car and just push them into normal traffic. They take whatever streets are open, maybe arrive jumbled — but the roads are shared so nothing is wasted. Virtual circuit: you first drive once to mark a route with little colored stickers at each crossroad. Then your cars just follow the stickers (cheap to read) and stay in order — but other people's cars still use the same roads.

Connections

Computer Networks
Routing Algorithms (datagram needs routing tables; VC needs setup signaling)
Multiplexing — TDM, FDM (how circuits reserve channels)
TCP — reliable ordered delivery (fixes datagram reordering)
MPLS / ATM (real virtual-circuit technologies)
Store-and-Forward and Network Delays
Queueing Delay

Flashcards

What are the three phases of circuit switching?

Setup, data transfer, teardown.

Why does circuit switching delay have only ONE

L/R

term, not

d\cdot L/R

After setup the path is a dedicated pipe — no store-and-forward, so the message transmits once and propagates; hops only add propagation

d\,t_p

Datagram delay for 1 packet over

d

links?

d\cdot\frac{L}{R} + d\,t_p

(store-and-forward replays

L/R

at each hop).

Pipelined datagram delay for

P

packets?

\frac{d+P-1}{P}\cdot\frac{L}{R} + d\,t_p

; as

P\to\infty

transmission →

L/R

Why do smaller packets reduce delay?

More packets ⇒ more pipelining overlap across links, so effective transmission approaches a single-hop

L/R

(until header overhead dominates).

What does a switch carry in a datagram packet vs a VC packet?

Datagram: full destination address. VC: a small locally-meaningful label/VC number.

What is label swapping?

At each hop a switch maps (in link, in VC#) → (out link, out VC#) and replaces the label, forwarding by table lookup.

Does a virtual circuit reserve bandwidth?

No — it reserves a logical path and installs labels; bandwidth is still shared (statistically multiplexed).

Which switching methods preserve packet order?

Circuit and virtual circuit (single fixed path); datagram does not.

What state does each switch keep?

Circuit: per-circuit reservation. Datagram: per-destination routing table. VC: per-virtual-circuit table entry.

Two real technologies using virtual circuits?

ATM, Frame Relay, MPLS (any two).

When is circuit switching wasteful?

For bursty traffic — reserved bandwidth sits idle during silent periods, blocking others.

Concept Map

Hinglish (regional understanding)

Intuition Hinglish mein samjho

Switching ka matlab simple hai: network ek bada sheher hai jisme bahut saare crossroads (switches) hain, aur humein decide karna hai ki data ko kaunse raste se bheja jaaye. Iska teen tareeke hote hain. Circuit switching phone call jaisa hai — pehle pura raasta reserve kar lo (setup), phi aaram se baat karo, phir hang up (teardown). Iska fayda: ek hi baar transmission cost ( $L/R$ ) lagti hai kyunki har switch pe packet ruk-ruk ke store nahi hota. Nuksaan: bandwidth reserve rehti hai, aur agar tum chup ho to wo waste ho rahi hai.

Packet switching (datagram) mein data ko chhote tukdo (packets) mein todte hain, har packet pe poora destination address likha hota hai, aur har packet alag-alag raste se ja sakta hai. Problem ye hai ki har hop pe "store-and-forward" hota hai — switch pura packet receive karke phir aage bhejta hai, isliye 1 packet ka delay $d\cdot L/R$ ban jaata hai. Lekin trick ye hai: agar bahut saare chhote packets bhejo to pipelining hoti hai — jab link 2 pe packet 1 chal raha hota hai, link 1 pe packet 2 already chal raha hota hai. Isse effective transmission ghatkar lagbhag $L/R$ reh jaati hai. Yahi reason hai ki internet packet switching use karta hai.

Virtual circuit dono ka mix hai — best of both worlds. Pehle ek baar setup karke har switch mein chhota sa label (VC number) install kar dete hain. Phir packets sirf label dekhke forward hote hain (full address nahi chahiye), aur sabhi ek hi raste se in-order jaate hain. Important baat: VC mein bandwidth reserve nahi hoti — sirf logical path fix hota hai. ATM, Frame Relay, MPLS isi pe based hain.

Yaad rakhne ka mantra: Call = Circuit, Mail = Packet, Tour = Virtual Circuit. Exam mein delay formulas ko ratne ki jagah unka why samjho — circuit mein store-and-forward nahi hota isliye sirf ek $L/R$ ; datagram mein hota hai isliye $d\cdot L/R$ ; aur pipelining se $\frac{d+P-1}{P}\cdot\frac{L}{R}$ .